1. Field of the Invention
This invention is related to the field of register files and other memory circuits.
2. Description of the Related Art
Register files and other memory circuits are used as storage for a wide variety of purposes in integrated circuits. For example, in processors, register files may be used to implement various sets of architected registers (that is, registers specified in the instruction set architecture implemented by the processor). Processors that implement register renaming or other speculative execution techniques may implement register files to store speculative register contents. Furthermore, register files may be used to implement queues, first-in first-out (FIFO) buffers, other buffers, state storage for various implementation-specific circuits, etc.
Standard register file/memory circuit design includes a set of memory cells arranged into one or more arrays of rows and columns. Each column of memory cells stores the same bit position of different array entries, and the rows form the entries. Multiple bits read from/written to an entry as a unit are often generically referred to as a “word” of the array. Thus, the control signals provided to the array to read/write an entry are referred to as “wordlines”. Each column of memory cells are connected to a pair of bitlines for each read port and write port on the array. An address is provided on the read port, and the entry selected by that address has its wordline activated. The wordline controls two passgate transistors within the memory cell that connect the memory cell to the bitlines, and the memory cell develops a differential on the bitlines that represents the stored bit. A senseamplifier circuit detects the differential and amplifies it to provide the output bit from the column.
The bitlines in the standard design are typically long and highly capacitive, and precharging the bitlines and discharging them for reads consumes significant power. Each read port adds additional sets of bitlines, further increasing the power consumption. Furthermore, since the memory cells must sink charge to discharge one of the bitlines to develop the differential, adding read ports adds stress to the memory cell design. Adding read ports changes the design of the memory cell itself, since transistors must be added to connect the memory cell to more bitlines and more wordlines must be added to the cell. As read ports (and write ports) are increased in a given design, the amount of area required for a memory cell often increases and in many cases may be dominated by the area required to wire the wordlines and bitlines to the memory cells.